1. Field of Invention
The present invention relates to a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof; particularly, it relates to such DMOS device and manufacturing method wherein the breakdown voltage is increased.
2. Description of Related Art
FIGS. 1A-1B show a cross-section view and a 3D (3-dimensional) view of a prior art double diffused metal oxide semiconductor (DMOS) device 100 respectively. As shown in FIGS. 1A and 1B, a P-type substrate 11 has multiple isolation regions 12 by which a device region of the DMOS device 100 is defined. The isolation regions 12 and a field oxide layer 12 for example are a local oxidation of silicon (LOCOS) structure or a shallow trench isolation (STI) structure, the former being shown in the figures. The DMOS device 100 includes an N-type well 14, a gate 13, a drain 15, a source 16, a body region 17, a body electrode 17a, and the field oxide layer 12a. The well 14, drain 15 and the source 16 are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation process step implants N-type impurities to the defined region in the form of accelerated ions. The drain 15 and the source 16 are beneath the gate 13 and at different sides thereof respectively. The body region 17 and the body electrode 17a are formed by lithography process steps and ion implantation process steps, wherein the lithography process step defines the implantation region by a photoresist mask together with a self-alignment effect provided by all or part of the gate 13, and the ion implantation process step implants P-type impurities to the defined region in the form of accelerated ions. Part of the gate 13 is above the isolation region 12 in the DMOS device 100.
The DMOS device is a high voltage device designed for applications requiring higher operation voltages. However, if it is required for the DMOS device to be integrated with a low voltage device in one substrate, the DMOS device and the low voltage device should adopt the same manufacturing process steps with the same ion implantation parameters, or the DMOS device is required to be manufactured in a non-epitaxial silicon substrate, and thus the flexibility of the ion implantation parameters or the performance for the DMOS device is limited; as a result, the DMOS device will have a lower breakdown voltage and therefore a limited application range. To increase the breakdown voltage of the DMOS device, additional manufacturing process steps are required, or as a typical high voltage device, an epitaxial silicon substrate is provided; that is, an additional lithography process step and an additional ion implantation process step in order to provide different ion implantation parameters are required, or a more expensive substrate is required, but both ways increase the cost.
In view of above, to overcome the drawbacks in the prior art, the present invention proposes a DMOS device and a manufacturing method thereof which increases the breakdown voltage so that the DMOS device may have a broader application range, in which an additional lithography process step and the epitaxial substrate are not required such that the DMOS device can be integrated with and a low voltage device and manufactured by common manufacturing process steps.